Idle Circuits Make Light Work

Innovative power recycling technique could revolutionize electronics.

As electronic devices become smaller and more powerful, managing their energy consumption is crucial for extending battery life, reducing data center operating costs and decreasing environmental impact.

Ioannis Savidis, PhD, associate professor of electrical and computer engineering, and his team in the Integrated Circuits and Electronics (ICE) Design and Analysis Lab are developing innovative techniques to recycle power that would otherwise be wasted inside microprocessors and systems-on-chips (SoCs).

Inside the microprocessors that power our devices, electricity flows even when components are inactive. In the past, techniques like clock gating and power gating – that is, powering down inactive components – have been used to curb energy waste. “These methods save power, but leakage remains a major unresolved issue,” noted Savidis.

Rather than simply shutting down idle circuits, Savidis’ technique repurposes them to do useful work powering lower voltage components. This allows new processing capabilities to be added at low cost.

“Recycling leakage for useful computation has the potential to significantly move the needle on energy efficiency,” he explained.

Savidis’ technique works by dividing a microchip into active blocks that run programs and idle blocks that leakage can be tapped from. Special switches route current from idle blocks into a ‘virtual ground’ that powers a low-energy subsystem, recycling energy rather than losing it as heat as current is dumped to true ground.

“Imagine two buckets connected by a tube,” Savidis said. “When the top bucket has spare water, it can flow to fill the bottom bucket.”

A key innovation enabling efficient leakage recycling is the use of an algorithm that was developed by Savidis’ team called longest idle time-leakage recycling (LIT-LR) that schedules which idle blocks to tap at any time. The algorithm monitors downtime and prioritizes blocks based on idleness. Blocks idle for long periods supply the leakage current, while briefly inactive blocks are avoided to minimize unnecessary switching between the recycling and non-recycling state, which is energy inefficient. In addition, the needed transistor switches account for up to 12% of total power in modern processors; therefore, improving switch efficiency unlocks large additional energy savings.

“Intelligently pairing idle blocks with active components is crucial to maximizing benefits,” explained Savidis. “Otherwise, you risk negatively impacting performance as well as energy efficiency.”

In simulations, LIT-LR reduced switching energy by 25% compared to random idle block selection. Peak power also fell by over 7% using the tailored algorithm. Savidis’ team has powered circuits at one-third the normal voltage using recycled leakage in simulations.

The enhanced efficiency unlocked by Savidis’ research provides wide-ranging benefits for both manufacturers and end users of electronic devices.

For device makers, recycling leakage current allows adding more computational capabilities without sacrificing battery life or generating additional heat. Higher-performance laptops and smartphones can incorporate more advanced features while maintaining portability and charge duration. Leakage recycling also reduces costs for data center operators by allowing computation at lower voltages for applications with low computing demand.

Consumers stand to gain extended battery life for portable electronics before needing a recharge. Plus, power savings ultimately translate to lower prices over time. “Greater energy efficiency benefits manufacturers initially through expanded product capabilities, then consumers as those gains scale up,” explained Savidis.

On the sustainability front, improved energy efficiency directly reduces the carbon footprint of electronic devices by curbing wasted power usage. “Improving efficiency allows us to do more with less,” noted Savidis, “which benefits the environment long-term.”

Including these kinds of efficiencies in microprocessors and SoCs pushes the boundaries of what has already become an increasingly complex field of circuit design. Each new generation of chips must pack more computing into smaller spaces while minimizing delays and improving power savings. To that end, an area of emerging interest in Savidis’ research focuses on developing machine learning techniques for circuit design.

Machine learning can provide more accurate early estimates of factors like timing and interconnect impedance before a final design is completed. This reduces the need for extensive late-stage simulations and design recycles, where design engineers must return to earlier stages and modify the circuit to correct for missed performance and power targets.
“With traditional design, you may only discover a timing violation in later testing stages, and you have to go back and reiterate through your design to be able to meet whatever timing constraints you might have,” Savidis explained. This iterative process takes considerable time and resources.

To enable their research, Savidis’ team needs large datasets rep- resenting circuits to train and validate models. They developed a flexible framework that quickly generates circuit layouts using an automated physical design process. By controlling parameters like component connectivity, they can easily generate thousands of unique circuit graphs and process reports. This data trains machine learning models models to predict timing, impedance, power and other characteristics.

In a recent paper, Savidis showed neural networks trained on circuit graphs can make performance predictions for a new unseen

chip design. Fine-tuning the networks with a small sample of data from the new design improves accuracy. This highlights the value of their graph framework for capturing topological features to develop machine learning techniques.

The potential benefits of the practice are far-reaching. Even if machine learning can’t fully automate tasks, the gains in efficiency can be substantial. “The hope would be that machine learning might not deliver your ultimate solution, as you still have to run certain checks that traditional tools are required for,” Savidis emphasized. “But if you only have to go through three iterations of a design instead of 15, that’s a significant time savings, and you can get your product to market faster.”

Savidis’ innovative research on recycling wasted energy and applying machine learning to circuit design exemplify his creative approach to problem-solving. His cross-disciplinary team combines expertise in digital and analog circuits, low-power design, machine learning and beyond to push boundaries in efficiency and automation. While challenges remain, their progress developing novel techniques like leakage recycling and machine learning-enabled circuit design pave the way for more powerful and sustainable electronics.

“By improving energy efficiency and leveraging AI, we can continue advancing technology while ensuring it benefits both consumers and the planet,” Savidis said.