PhD Defense: Instrumenting and analyzing platform-independent communication in applications
Tuesday, March 3, 2015
2:00 PM-4:00 PM
Presenter: Siddharth Nilakantan
Advisor: Dr. Mark Hempstead
Abstract
The performance of microprocessors is limited by communication. This limitation, sometimes alluded to as the memory wall, refers to the hardware-level cost of communicating with memory. Recent studies have found that the promise of speedup from transistor scaling, or employing heterogeneous processors, such as GPUs, is diminished when such hardware communication costs are included.
Based on the insight that hardware communication at run-time is a manifestation of communication in software, this dissertation proposes that automatically capturing and classifying software-level communication is the first step in performing fast, early-stage design space exploration of future multicore systems. Software-level communication refers to the exchange of data between software entities such as functions, threads or basic blocks. Communication classification helps differentiate the first-time use from the reuse of communicated data, and distinguishes between communication external to a software entity and local communication within a software entity. We present Sigil, a novel tool that automatically captures and classifies software-level communication in an efficient way.
Due to its platform-independent nature, software-level communication can be useful during the early-stage design of future multicore systems. Using the two different representations of output data that Sigil produces, we show that the measurement of software-level communication can be used to analyze i) function-level interaction in single-threaded programs to determine which specialized logic can be included in future heterogeneous multicore systems, and ii) thread-level interaction in multi-threaded programs to aid in chip multi-processor(CMP) design space exploration. We employ Sigil's function-level communication profiles to find candidate software functions for specialization, and to perform a novel study on allocation of chip area amongst candidates. We also show a novel study that uses Sigil's thread-level communication profiles to generate traces of multi-threaded programs and employ the traces for fast and accurate design space exploration of CMPs.
Contact Information
Electrical and Computer Engineering Department
215-895-2241
ece@drexel.edu